1. Field of the Invention
The present invention relates to an active matrix type image display unit using a thin-film transistor and to a method for manufacturing the same. In particular, the invention relates to an image display unit using a thin-film transistor by reducing the number of processes for ion implantation and photolithography in the preparation of the thin-film transistor. The invention also relates to a method for manufacturing the same.
2. Description of the Prior Art
In an active matrix type image display unit, an active element represented by a thin-film transistor is prepared on an insulating substrate made of glass or the like in a pixel circuit and in peripheral circuits for driving the pixel circuit. As the active matrix type image display unit, a liquid crystal display unit or an organic EL display unit is widely used in practical application or is now on the stage toward practical application. Here, the description is given on the liquid crystal display unit and the organic EL display unit as examples, while it is needless to say that this can be applied to the other active matrix type image display unit, which is based on different concept of display.
A thin-film transistor (also referred as “TFT”) using polysilicon exhibits the mobility by two digits or more higher than the TFT using amorphous silicon. As an example to provide such characteristics, an active matrix type liquid crystal display unit described in the Non-patent Document 1 may be cited. This image display unit is a flat type image display unit called “flat panel display” (FPD). By designing a part of peripheral circuits (such as driving circuits) of this display unit as polysilicon TFT, the number of connecting terminals between pixel area and the peripheral circuits can be reduced, and a high-precision image display can be accomplished.
FIG. 29 is a circuit diagram of a liquid crystal display unit, which is an example of the image display unit according to the prior art. FIG. 30 (a) is a plan view of the thin-film transistor to constitute peripheral circuits (a data line driving circuit DDR and a gate line driving circuit GDR) in FIG. 29, and FIG. 30 (b) is a plan view of a pixel area PXL. FIG. 31 represents cross-sectional drawings along the lines A-A′, B-B′, and C-C′ in FIG. 30 respectively. FIG. 32 to FIG. 39 each represents a process drawing of a PMOSTFT region, a NMOSTFT region and a storage capacitor Cst shown in FIG. 31 respectively. In FIG. 32 to FIG. 39, the NMOSTFT region is shown at the left in each of the drawings, and the PMOSTFT region is shown at the center of each of the drawings. The NMOSTFT and the storage capacitor Cst are shown at the left in each of the drawings. The details as described above are given only in FIG. 32.
As the thin-film transistor, a top gate type low temperature polysilicon TFT is used. The gate electrode is made of a type of non-transparent metal film. The PMOSTFT, the NMOSTFT and the top electrode of the storage capacitor Cst have the same thickness.
The pixel area PXL comprises a TFT (NMOSTFT), a storage capacitor Cst, and a liquid crystal LC, and it is driven by a signal sent via a data line DL, a gate line GL and a capacity line CL from a data line driving circuit DDR and a gate line driving circuit GDR. A high density n-type polysilicon layer and a gate line electrode layer are used in the bottom electrode and the top electrode of the storage capacitor. The peripheral circuit comprises NMOSTFT and PMOSTFT.
The method for manufacturing this liquid crystal display unit is as follows: On an insulating substrate SUB preferably made of glass plate, a laminated film BUF of silicon nitride and silicon oxide is deposited in thickness of 100 nm as a buffer layer (an underlying film). Further, an amorphous silicon layer is deposited in thickness of 50 nm by the plasma CVD method. Next, XeCl excimer laser is projected to crystallize the amorphous silicon layer. Then, dry etching is performed by using resist (prepared by patterning in photolithographic process already known) as a mask, and a polysilicon layer PSI in island-like shape is obtained. Next, a gate insulator film GI is deposited in thickness of 100 nm by the plasma CVD method (deposition of the gate insulator film) (FIG. 32).
Ion implantation for threshold adjustment of NMOSTFT is performed over the entire surface, and low density p-type region LDP is prepared. The second photolithographic process is performed, and ion implantation for threshold adjustment of PMOSTFT (low density n-type implantation LDN) is carried out only on the region where PMOSTFT is to be prepared (FIG. 33).
The third photolithographic process is performed, and ion implantation is carried out on the bottom electrode of the storage capacitor Cst. This ion implantation is high density n-type ion implantation (HDN) (FIG. 34).
A gate metal film is deposited, and the fourth photolithographic process is performed. By wet etching, a gate electrode GT is prepared. In this case, over-etching is performed so that contour of the metal film of the gate electrode is moved back toward inner side by about 1 μm compared with contour of the resist RST (FIG. 35).
By using the resist RST shown in FIG. 35 as a mask, high density n-type source-drain ion implantation (HDN) is carried out. Next, the resist RST is removed, and low density n-type LDD (Lightly Doped Drain) ion implantation (LDN) is performed. In general, NMOSTFT has high leakage current, and the leakage current is suppressed through alleviation of electric field by providing LDD region. Hot carrier resistance can be improved by the alleviation of electric field (FIG. 36).
The fifth photolithographic process is performed, and high density p-type ion implantation (HDP) is carried out only on PMOSTFT (FIG. 37).
An interlayer insulator film INS1 is deposited. The sixth photolithographic process is performed, and a contact hole is formed by dry or wet etching. Metal for wiring is deposited. The seventh photolithographic process is performed, and the source-drain electrodes SD are prepared by dry or wet etching (FIG. 38).
An interlayer insulator film INS2 and a protective insulator film PAS are deposited. The eighth photolithographic process is performed, and a contact hole is formed. A transparent conductive film for pixel electrode is deposited. The ninth photolithographic process is preformed, and a pixel electrode PX is prepared (FIG. 39).
The prior art of this type is disclosed in the Non-Patent Document 1.    [Non-Patent Document 1] The Society for Information Display International Symposium; Digest of Technical Papers, p. 172; 1999.